Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from Arm®, including the AXI4-Lite control register interface subset.
Included at no additional charge with Vivado™ and ISE™ Design Suite.
The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from Arm®, including the AXI4-Lite control register interface subset. The Interconnect IP is intended for memory-mapped transfers only; AXI4-Stream transfers are not applicable. The AXI Interconnect IP can be used from the Vivado IP catalog as a pcore from the Embedded Development ToolKit (EDK™) or as a standalone core from the CORE Generator™ IP catalog.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI Interconnect | v2.1 | AXI4 AXI4-Lite AXI3 |
Vivado™ 2022.1 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Artix™ 7 Kintex 7 / -2L Virtex 7 / -2L / XT |
AXI Interconnect | v1.06a | AXI4 AXI4-Lite AXI3 |
ISE™ 14.1 EDK™ 14.1 |
Zynq 7000 Artix 7 Kintex 7 / -2L Virtex 7 / -2L / XT Virtex 6 CXT / HXT / SXT / LXT/ -1L Virtex 5 FXT / LXT / SXT / TXT Virtex 4 FX / LX / SX Spartan™ 6 LX / LX |
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