Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe® TLP packets and PCIe requests to AXI4 commands.
The AXI PCIe® Gen 3 Subsystem core provides an interface between the AXI4 interface and the Gen 3 PCI Express® (PCIe) silicon hard core. The AXI4 PCIe sub-system provides full bridge functionality between the AXI4 architecture and the PCIe network. The sub-system is composed of the PCIe core, the GT interface and the AXI4 interface. The bridge circuit is implemented in the FPGA fabric and the PCIe core and GT are integrated elements in the FPGA.
The AXI4 PCIe core provides a transaction level translation of AXI4 commands to PCIe TLP packets and PCIe requests to AXI4 commands.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI Bridge for PCI Express® (PCIe®) Gen3 Subsystem |
v3.0 | AXI4 | Vivado™ 2024.1 | Kintex™ UltraScale™ Virtex™ UltraScale Virtex 7 XT |
DMA/Bridge Subsystem for PCIe in AXI Bridge Mode |
v3.0 | AXI4 | Vivado 2024.1 | Kintex 7 UltraScale+™ Virtex 7 UltraScale+ Zynq™ 7000 UltraScale+ |
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