Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The FIFO Generator core is a fully verified first-in, first-out (FIFO) memory queue ideal for applications require in-order data storage and retrieval.
The LogiCORE™ IP FIFO Generator core generates fully verified first-in, first-out (FIFO) memory queues ideal for applications requiring in-order data storage and retrieval.
The core provides an optimized solution for all FIFO configurations and delivers maximum performance (up to 500 MHz) while utilizing minimal resources. Delivered through the Vivado™ Design Suite, the structure can be customized by the user including the width, depth, status flags, memory type, and the write/read port aspect ratios.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
FIFO Generator | v13.2 | AXI4 AXI-Stream AXI4-Lite AXI3 |
Vivado™ 2017.3 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 / -2L Kintex 7 / -2L Virtex 7 / -2L / XT / -2G |
FIFO Generator | v9.3 | AXI-Stream AXI-Stream AXI4-Lite AXI3 |
ISE™ 14.3 / 14.4 | Zynq 7000 Artix 7 / -2L Kintex 7 / -2L Virtex 7 / -2L / XT / -2G Virtex 6 CXT / HXT / LXT / SXT / -1L Spartan™ 6 LX / LXT / -1L Virtex 6 CXT / HXT / LXT / SXT / -1L |
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