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UltraScale+™ Device Integrated Block for PCI Express® (PCIe®)

Design Tools Support: Vivado Software
Bundled With: Vivado Software
License: End User License Agreement
Device Support: Virtex UltraScale+, Kintex UltraScale+, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

The AMD UltraScale+™ FPGA Integrated Block for PCI Express® solution IP core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with UltraScale+ devices. The Integrated Block for PCI Express (PCIe®) solution supports 1-lane, 2-lane, 4-lane, 8-lane, and 16-lane Endpoint configurations, including Gen1 (2.5 GT/s), Gen2 (5.0 GT/s) and Gen3 (8 GT/s) speeds. This solution supports the AXI4-Stream.

Key Features and Benefits

Designed to PCI Express Base Specification 3.1
PCI Express Endpoint, Legacy Endpoint or Root Port Port Modes
x1, x2, x4, x8 or x16 link widths
Gen1, Gen2 and Gen3 link speeds
PHY only mode available
AXI4 Streaming Interface to customer logic
- Configurable 64-bit/128-bit/256-bit/512-bit data path widths
- Four Independent Initiator/Target, Request/Completion Streams
Parity protection on internal logic data paths and data interfaces
Advanced Error Reporting (AER) and End-to-End CRC (ECRC)

Resource Utilization

UltraScale+ PCI Express Integrated Block Resource Utilization

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG213 - UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213) (v1.3)

The core is a high-bandwidth, scalable, and reliable serial interconnect building block solution for use with AMD UltraScale+™ architecture-based devices.

View Product Guide