Design Flow Assistant
Interactive guide to help you create a development strategy.
Delivering Breakthrough AI Performance/Watt for Automotive Applications
The automotive grade (XA) Versal AI Edge series is the first 7 nm product from AMD to be auto-qualified—optimized for automotive applications such as automated driving and advanced driver assistance systems (ADAS).
Versal AI Edge XA adaptive SoCs accelerate the whole application from sensor to AI, with the latest safety security standards required by OEMs and Tier 1 manufacturers. Versal AI Edge XA devices can handle multiple different sensor types and shift compute from edge sensors to central compute modules.
Offering flexible, high-performance AI inference via AI Engines, Versal AI Edge XA devices handle high bandwidth at low latency via a flexible interconnect and heterogenous compute.
The Versal architecture delivers breakthrough AI performance/watt for automotive applications, enabling integration of any sensor, connectivity to any interface, and flexibility to handle any workload.
Versal AI Engines can implement sensor fusion and machine learning algorithms, accelerate pre– and post-data processing across the pipeline, and implement motor control for real-time response.
AI Engines support a breadth of workloads common in automotive applications, including AI inference, image processing, and motion control.
Safety and security features are critical to automotive applications. Versal AI Edge XA adaptive SoCs help meet various safety and security requirements.
The Versal architecture is partitioned with safety features in each domain and provides global resources to monitor and help reduce common cause failures.
New security features over previous-generation adaptive SoCs include higher bandwidth AES & SHA encryption/decryption as well as glitch detection, helping to improve protection against cloning, IP theft, and cyber attacks.
The Versal adaptive SoC’s programmable I/O allows connection to any sensor or interface, as well as the ability to scale for future interface requirements. Designers can configure the same I/O for either sensors, memory, or network connectivity, and budget device pins as needed. Different I/O types provide a wide range of speeds and voltages for both legacy and next-generation standards.
XAVE2002 | XAVE2102 | XAVE2202 | XAVE2302 | XAVE1752 | XAVE2602 | XAVE2802 | |
---|---|---|---|---|---|---|---|
AI Engine ML | 8 | 12 | 24 | 34 | 0 | 152 | 304 |
AI Engines | 0 | 0 | 0 | 0 | 304 | 0 | 0 |
DSP Engines | 90 | 176 | 324 | 464 | 1,312 | 984 | 1,312 |
System Logic Cells | 43,750 | 80,080 | 229,688 | 328,720 | 981,120 | 820,313 | 1,139,040 |
LUTs | 20,000 | 36,608 | 105,000 | 150,272 | 448,512 | 375,000 | 520,704 |
Accelerator RAM (Mb) | 32 | 32 | 32 | 32 | 0 | 0 | 0 |
Total Memory (Mb) | 40.2 | 48 | 69.4 | 85.6 | 177.1 | 91.1 | 111.3 |
NoC Master / NoC Slave Ports | 2 | 2 | 5 | 5 | 21 | 21 | 21 |
PCIe® w/ DMA (CPM) | - | - | - | 1 x Gen4x16 | 1 x Gen4x16 | 1 x Gen4x16 | |
PCI Express® | - | 1 x Gen4x8 | 1 x Gen4x8 | 4 x Gen4x8 | 4 x Gen4x8 | 4 x Gen4x8 | |
40G Multirate Ethernet MAC | 0 | 1 | 1 | 2 | 2 | 2 | |
Video Decoder Engines (VDEs) | - | - | - | - | 2 | 4 | |
GTY Transceivers | 0 | 0 | 0 | 0 | 44 | 0 | 0 |
GTYP Transceivers | 0 | 0 | 8 | 8 | 0 | 32 | 32(1) |
Application Processing Unit | Dual-core Arm® Cortex-A72 processor, 48 KB/32 KB L1 cache w/ parity & ECC; 1 MB L2 cache w/ ECC | ||||||
Real-time Processing Unit | Dual-core Arm Cortex-R5F processor, 32 KB/32 KB L1 cache, and 256 KB TCM w/ECC | ||||||
Memory | 256 KB on-chip memory w/ECC | ||||||
Connectivity | Ethernet (x2); UART (x2); CAN-FD (x2); USB 2.0 (x1); SPI (x2); I2C (x2) |
Join the Versal adaptive SoC notification list to receive the latest news and updates.