ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
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LD-based Parallel Latch
par: AMD
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.
- Design Tools Support: ISE Design Suite
- Bundled With: ISE Design Suite
- Device Support: Spartan 3, Spartan 3E, Virtex FPGAs, Virtex E, Virtex II, Virtex II Pro