ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
por: AMD
The OPB IPIF/ V3 PCI™ Core Bridge design bridges the OPB IPIF (On-Chip Peripheral Bus Intellectual Property Interface) and the PCI64 Interface v3.0 core providing full bridge functionality between the AMD 32-bit OPB and a 32-bit V2.2 compliant PCI (Peripheral Component Interconnect) bus.
The OPB IPIF/ V3 PCI Core Bridge design bridges the OPB IPIF (On-Chip Peripheral Bus Intellectual Property Interface) and the PCI64 Interface v3.0 core providing full bridge functionality between the AMD 32-bit OPB and a 32-bit V2.2 compliant PCI (Peripheral Component Interconnect) bus. Only 33/66 MHz, 32-bit PCI buses are supported at this time. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit. The OPB to PCI™ 32/33 Bridge is offered as an evaluation core in the EDK™. To generate a full OPB to PCI license, the PCI-32 LogiCORE™ must be purchased. Available to all licensees of the PCI32 LogiCORE IP cores.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.