• Course Information

    Description

    This course provides professors necessary skills to design and debug a system using Vivado™ IP Integrator, hardware analyzer, and Vivado HLS.

    Level

    Intermediate

    Duration

    2 Days

    Who Should Attend

    Professors who are familiar with AMD programmable technology and wish to get up to speed with SoC-based system design using Zynq™.

    Pre-requisites

    Digital logic and FPGA design experience
    Basic experience with Vivado Design Suite
    Basic understanding of C programming

Skills Gained

After completing this workshop, you will be able to:

  • Use AMD Design Constraints to communicate performance
  • Rapidly architect an embedded system targeting the ARM processor of Zynq located on ZedBoard using Vivado and IP Integrator
  • Extend the hardware system with AMD provided peripherals
  • Create a custom peripheral and add it to the system
  • Debug a design using Vivado hardware analyzer
  • Use Vivado HLS to generate an IP-XACT compliant hardware accelerator

Course Overview

Day 1:

  • 7-Series Architecture Overview

  • Vivado Design Flow

  • Lab 1: Creating an HDL Design
    • Use Vivado IDE to create a simple HDL design. Simulate the design using the XSIM HDL simulator available in Vivado design suite. Generate the bitstream and verify in hardware.
       
  • AMD Design Constraints

  • Lab 2: AMD Design Constraints
    • Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Then create the timing constraints and perform the timing analysis.
       
  • IP Integrator and Embedded System Design Flow

  • Lab 3: Create a Processor System using IP Integrator
    • Create a simple ARM Cortex-A9 based processor design targeting the ZedBoard using IP Integrator.

Day 2:

  • Embedded System Design with Custom IP

  • Lab 4: Creating and Adding Your Own Custom IP
    • Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral. Write a basic C application to access the peripherals.
       
  • System Debugging using Vivado Logic Analyzer and SDK

  • Lab 5: Debugging using Vivado Logic Analyzer cores
    • Insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
       
  • Profiling and Performance Improvement

  • Introduction to High-Level Synthesis with Vivado HLS

  • Improving Performance and Resource Utilization

  • Creating an Accelerator

  • Lab 6: Creating a Processor System using Accelerator
    • Profile an application performing a function both in software and hardware. Create an accelerator in Vivado HLS. Use the generated accelerator to build a complete system.

Common to ZedBoard and ZYBO

ZedBoard

ZYBO

Common to ZedBoard and Zybo

ZedBoard

Zybo