Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The Integrated Logic Analyzer (ILA) IP with AXIS interface is a configurable logic analyzer core that can debug and monitor internal signals and AXI interfaces within a design.
The Integrated Logic Analyzer (ILA) IP with AXIS interface is a configurable logic analyzer core that can debug and monitor internal signals and AXI interfaces within a design. The ILA core includes many advanced features such as Boolean trigger equations and edge transition triggers. It can not only be used for triggering on events and capturing the data from internal signals but also be used for transaction-level debug of one or more AXI interfaces (AXI4-MM or AXI4-S).
The ILA IP has a dedicated AXIS interface for connection to a debug master interface or core (such as Debug Hub) for software communication and control/status management.
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