Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
发布者: AMD
The LogiCORE™ 50G IEEE 802.3 RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer.
AMD offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the 25G/50G Ethernet Consortium Schedule 3 specification and connects seamlessly to the AMD soft 50G Ethernet Subsystem IP on UltraScale™, Virtex UltraScale+™, Kintex™ UltraScale+, and Zynq™ UltraScale+ devices.
Hardware Evaluation Time Out Period * : ~ 8 hrs
LogiCORE™ | Version | AXI Support | Software Support | Supported Device Families |
---|---|---|---|---|
50G IEEE 802.3 Reed-Solomon Forward Error Correction | v2.0 | AXI4-Lite | Vivado™ 2019.1 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Virtex UltraScale™ |
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