The Versal™ adaptive SoC DMA and Bridge Subsystem for PCIe® provides a rich set of options for high performance data transfer between a Versal adaptive SoC and other devices using the widely deployed and industry standard PCI Express® system architecture. This subsystem is implemented within the robust and flexible Versal adaptive SoC integrated block for PCI Express (PL PCIE4 or PL PCIE5). Three implementations are available:
QDMA – A queue based, configurable scatter-gather DMA implementation which provides thousands of queues, support for multiple physical/virtual functions with single-root I/O virtualization (SR-IOV), and advanced interrupt support. In this mode the IP provides AXI4-MM and AXI4-Stream user interfaces which may be configured on a per-queue basis. Based on PCIe system architecture conventions, the QDMA is highly suitable for endpoint (EP) use cases and may also be used to construct proprietary system architectures.
AXI Bridge – A bridge based, configurable translation level between the PCIe system and AXI4-MM internal to the AMD device. In this mode the IP translates and forwards PCIe read and write accesses into AXI4-MM interface commands, and conversely translates and forwards AXI4-MM interface commands into PCIe read and write accesses. Based on PCIe system architecture conventions, the AXI Bridge is highly suitable for root port (RP) use cases as well as endpoint (EP) use cases and may also be used to construct proprietary system architectures.
XDMA (PL PCIE4 only) – A channel based, configurable scatter-gather DMA implementation which provides four card-to-host (C2H) channels and four host-to-card (H2C) channels with interrupt support. In this mode the IP provides either AXI4-MM or AXI4-Stream user interfaces. Based on PCIe system architecture conventions, the XDMA is highly suitable for endpoint (EP) use cases and may also be used to construct proprietary system architectures.
