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Partial Reconfiguration Controller

作成者: AMD

The Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs. When hardware or software trigger events occur, the PRC pulls partial bitstreams from local memory and delivers them to the internal configuration access port (ICAP). The PRC also assists with logical decoupling and startup events, customizable per Reconfigurable Partition.

デザインツールサポート: Vivado Software
バンドル内容: Vivado Software
ライセンス: End User License Agreement
デバイスサポート: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ MPSoC, Zynq 7000

Overview
Documentation
Supported Tool Version

Product Description

The Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs. When hardware or software trigger events occur, the PRC pulls partial bitstreams from memory and delivers them to an internal configuration access port (ICAP). The PRC also assists with logical decoupling and startup events, customizable per Reconfigurable Partition.

This core is intended for enclosed systems where all of the Reconfigurable Modules are known to the controller. The optional AXI4-Lite register interface allows the core to be reconfigured at run time, so it can also be used in systems where the Reconfigurable Modules can change in a deployed system. The core can be customized for number of Virtual Sockets, number of Reconfigurable Modules per Virtual Sockets, operation and interface.

Key Features and Benefits

Support for up to 32 Virtual Sockets (Reconfigurable Partitions and periphery) and 128 Reconfigurable Modules per Virtual Socket
Up to 512 remapable software and hardware triggers per Virtual Socket
Optional hardware and software shutdown of Reconfigurable Modules (configurable per Reconfigurable Module)
Optional software start-up of Reconfigurable Modules (configurable per Reconfigurable Module)
Optional Reset of Reconfigurable Modules after loading (configurable per Reconfigurable Module)
Virtual Sockets can be shutdown and restarted by the user to allow external controllers to partially reconfigure the device
Compatible with AXI4-Lite and AXI4-Stream user interfaces

Resource Utilization

Partial Reconfiguration Controller Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

PG193 - Partial Reconfiguration Controller v1.3 Product Guide (PG193) (v1.3)

The AMD Partial Reconfiguration Controller core provides management functions for self-controlling partially reconfigurable designs.

View Product Guide