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XPS IIC Bus Interface

von: AMD

The XPS IIC Bus Interface provides a low speed, two wire, serial bus interface to a large number of popular devices.

Design Tools Support: ISE Design Suite
Bundled With: Embedded Development Kit
Lizenz: End User License Agreement
Device Support: Spartan 3, Spartan 3A, Spartan 3A DSP, Spartan 3E, Spartan 6, Virtex 4, Virtex 5, Virtex 6

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Overview
Documentation
Supported Tool Version

Product Description

Included in EDK™ at no additional charge starting in EDK9.2i.

This product specification defines the architecture, hardware (signal) interface, software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices.

Key Features and Benefits

Master or slave operation
Multi-master operation
Software selectable acknowledge bit
Arbitration lost interrupt with automatic mode switching from master to slave.
Calling address identification interrupt with automatic mode switching from master to slave
START and STOP signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus busy detection
Fast mode 400 KHz operation or standard mode 100 KHz
7 bit or 10 bit addressing
General call enable or disable
Transmit and receive FIFOs - 16 bytes deep
Throttling
General purpose output, 1 bit to 8 bits wide
Dynamic Start/Stop generation

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

DS606 - LogiCORE IP XPS IIC Bus Interface (v2.03a) Data Sheet (DS606) (v1.11)

View Data Sheet