Overview

Dynamic Function eXchange (DFX) allows designers to modify sections of a design while the rest of the design operates uninterrupted. With DFX, novel design techniques and features are made possible – these include flexible hardware acceleration, on-the-fly system updates, design collaboration, and fault tolerance. Dynamic Function eXchange follows the legacy of Partial Reconfiguration (PR), maximizing the flexibility of logical resources for over 20 years.

  • Pillar 1: Robust Design Flows
    Intuitive design methodologies with comprehensive device support
  • Pillar 2: IP Blocks for Ease of Implementation
    Foundational building blocks for ease of placement, reconfiguration, and debug
  • Pillar 3: Advanced Use Cases
    Leverage DFX technology for fast compile and team-based design

Features

DFX Intellectual Property (IP)

AMD offers four fundamental IP blocks for Dynamic Function eXchange in the Vivado Design Suite.

  • DFX Controller IP core intelligently manages real-time reconfiguration for up to 4096 modules with user-customizable hardware/software trigger events.
    • DFX Controller IP functions are supported for FPGA-based DFX designs only, as SoC DFX designs can be managed through software on the PS. 
  • DFX Decoupler IP core logically isolates the design from undefined behavior when a module is being reconfigured.
  • DFX AXI Shutdown Manager IP core isolates AXI interfaces from potentially erroneous transactions when a module is being reconfigured.
  • DFX Bitstream Monitor IP is a powerful debugging tool for FPGA partial bit files used in DFX. It can trace partial bit files from storage to the configuration engine, allowing bit file errors to be handled before reconfiguration. 

Advanced Use Cases

Abstract Shells:

Vivado Design Suite supports the abstract shell design flow for all UltraScale+ and Versal devices. Abstract shell design flows can reduce compilation time and memory usage for most designs.

  • Fast Compile Time
    • Abstract shell implementations are designed to deliver a decrease in compilation time and memory usage. See further details in WP533.  
  • Design Collaboration
    • Designers can hide proprietary IP in the obfuscated static region of abstract shell designs. External designers can then develop functionality in dynamic regions without access to proprietary information, helping to increase design collaboration security.
    • Dynamic logic can also interact with IP in the static region without triggering IP license checks.
      • (Disclaimer: must have redistributable rights for the IP) 

Tandem Configuration + DFX:

Tandem Configuration is a Vivado Design Suite feature that splits a design’s bitstream into two stages, allowing UltraScale, UltraScale+, and Versal devices to meet PCI Express® standards.

  • PCIe® Application Flexibility
    • Unlike standalone Tandem Configuration, any number of dynamic images can be reconfigured repeatedly after the initial two stage configuration (UltraScale and UltraScale+ devices only).
  • Bitstream Delivery Flexibility
    • Partial bitstreams for DFX can be delivered over PCIe® via QDMA or any configuration port (PCAP, MCAP, ICAP). 

Videos

Resources