AMBA 4 Open Specification
The AMBA® specifications define the interfaces and protocols, on-chip and off-chip, for use in applications across multiple market areas.
- Overview
- Documentation
- Key Benefits
- Details
- Supported Tool Versions
Product Description
AMBA® AXI4 (Advanced eXtensible Interface 4) is the fourth generation of the AMBA interface specification from Arm®. AMD Vivado™ Design Suite and ISE Design Suite extends the AMD platform design methodology with the semiconductor industry's first AXI4 Compliant Plug-and-Play IP.
For customers relying on IP to meet their Time-to-Market requirements for UltraScale™, 7 Series, Zynq™ 7000, Virtex™ 6 and Spartan™ 6 based designs, the AXI4 Plug-and-Play IP offers a single standard interface to make IP integration easier. AMD offers a broad set of AXI4 based IP with a single open standard interface across the Embedded, DSP, and Logic domains.
Higher Productivity
- Consolidates broad array of interfaces into one (AXI4), so users only need to know one family of interfaces
- Makes integrating IP from different domains, as well as developing your own or 3rd party partner IP easier
- Saves design effort because AXI4 IP are already optimized for the highest performance, maximum throughput and lowest latency
Greater Flexibility
- Supports Embedded, DSP and Logic Edition users
- Tailor the interconnect to meet system goals: Performance, Area, and Power
- Enables you to build the most compelling products for your target markets
Broad IP Availability
AMD worked closely with ARM to define the AXI4 specification for high-performance FPGA-based systems and designs. As part of our commitment to AXI4, AMD has adopted AXI4 as our next-generation IP interconnect standard for UltraScale, 7 Series, Zynq 7000, Spartan 6, Virtex 6 and future device families going forward
- AXI4 based Targeted Design Platforms help customers accelerate their Embedded Processing, DSP and Connectivity design development
- The AXI Reference Guide guides users through the transition to AXI4
Ecosystem Enablement
3rd party IP and EDA vendors everywhere have embraced the open AXI4 standard, helping to make it a widely adopted interface
- Cadence Design Systems, Inc., CAST, Inc., Siemens EDA, Synopsys, Inc., and Xylon d.o.o. are among those offering support for IP and tools which support the AXI4 interface
- This ensures a strong ecosystem for building AXI4-based system designs, driving ultimate productivity and faster time to market
Documentation
Key Benefits of AXI4 Interface
- AMD users will enjoy a wide range of benefits with the transition to AXI4 as a common user interface for IP. AXI4 is:
- Consistent: All interface subsets use the same transfer protocol
- Fully specified: Ready for adoption by customers
- Standardized: Includes standard models and checkers for designers to use
- Interface-decoupled: The interconnect is decoupled from the interface
- Extendable: AXI4 is open-ended to support future needs
- Additional benefits:
- Supports both memory mapped and streaming type interfaces
- Provides a unified interface on IP across communications, video, embedded and DSP functions
- Is easy to use, with features like automatic pipeline instantiation to help you more easily hit a specific performance target
- Is equal to or better than current solutions in key attributes, such as fMAX, LUT usage, latency, and bandwidth
- Enables AMD to efficiently deliver enhanced native memory, external memory interface and memory controller solutions across all application domains
AXI Details
AXI4
The AXI4 protocol is an update to AXI3 which is designed to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:
- Support for burst lengths up to 256 beats
- Quality of Service signaling
- Support for multiple region interfaces
AXI4-Lite
AXI4-Lite is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interfaces are:
- All transactions have a burst length of one
- All data accesses are the same size as the width of the data bus
- Exclusive accesses are not supported
AXI4-Stream
The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:
- Supports single and multiple data streams using the same set of shared wires
- Supports multiple data widths within the same interconnect
- Ideal for implementation in FPGAs
AXI4 IP Supported Tool Versions
AMD recommends that you use the latest version of LogiCORE™ IP cores whenever possible to access the latest enhancements and architecture support.
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| AXI4-Stream to Video Output v4.0 | 2017.3 | 14.3 (v2.01a) | AXI4-Stream |
| AXI Video Direct Memory Access v6.3 | 2017.3 | 14.4 (v5.04a) | AXI4 AXI4-Stream AXI4-Lite |
| Chroma Resampler v4.0 | 2015.4 | 14.3 (v3.01a) | AXI4-Stream |
| Color Correction Matrix v6.0 | 2015.4 | 14.3 (v5.01a) | AXI4-Stream AXI4-Lite |
| Color Filter Array Interpolation v7.0 | 2015.4 | 14.3 (v6.01a) | AXI4-Stream AXI4-Lite |
| Deinterlacer v4.0 | 2014.3 | 14.3 (v3.00a) | AXI4 AXI4-Stream AXI4-Lite |
| Gamma Correction v7.0 | 2015.4 | 14.3 (v6.01a) | AXI4-Stream AXI4-Lite |
| Gamma LUT v1.0 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| H.264/H.265 Video Codec Unit v1.0 | 2017.3 | AX84-Lite AXI4-MM |
|
| HDMI v3.0 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| Image Edge Enhancement v8.0 | 2015.4 | 14.4 (v6.00a) | AXI4-Stream AXI4-Lite |
| MIPI CSI Controller Subsystems (RX v3.1 - TX v2.0) |
2017.3 | AXI4-Stream AXI4-Lite |
|
| MIPI D-PHY v4.0 | 2017.3 | AXI4-Lite | |
| MIPI DSI Tx Controller Subsystem v2.0 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| On Screen Display v6.0 | 2015.4 | 14.4 (v5.01a) | AXI4-Stream AXI4-Lite |
| RGB to YCrCb Color Space Converterv7.1 | 2015.4 | 14.3 (v6.01a) |
AXI4-Stream AXI4-Lite |
| Sensor Demosaic v1.0 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| Test Pattern Generator v7.0 | 2017.1 | 14.4 (v4.00a) | AXI4-Stream AXI4-Lite |
| Video Frame Buffer Read and Video Frame Buffer Write v1.0 | 2017.3 | AXI4-Stream AXI4-Lite AXI4-MM |
|
| Video input to AXI4-Stream v4.0 | 2017.3 | 14.3 (v2.01a) | AXI4-Stream |
| Video Processing Subsystem v2.0 | 2017.3 | AXI4-Stream AXI4-Lite AXI4-MM |
|
| Video Timing Controller v6.1 | 2017.3 | 14.3 (v5.01a) | AXI4-Lite |
| YCrCb to RGB Color Space Converter v7.1 | 2015.4 | 14.3 (v6.01a) | AXI4-Stream AXI4-Lite |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| CAN v5.0 | 2015.4 | 14.4 (v4.2) | AXI4-Lite |
| CAN with Flexible Data Rate (CAN FD) v1.0 | 2016.3 | AXI4-Lite |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| Ethernet | |||
| 1G/10G/25G Switching Ethernet Subsystem v1.0 | 2017.3 | AXI4-Stream | |
| 10G Ethernet with 1588 Subsystem v3.1 | 2017.3 | AXI4-Lite AXI-Stream |
|
| 10 Gigabit Ethernet Media Access Controller (10GEMAC) v15.1 | 2017.3 | 14.5 (v11.6) | AXI4-Lite AXI-Stream |
| 10G/25G Ethernet Subsystem (25GEMAC / 25GBASE-KR) v2.3 | 2017.3 | AXI4 | |
| 40G/50G Ethernet Subsystem (50GEMAC / 50GBASE-KR2) v2.3 | 2017.3 |
AXI4-Stream | |
| Ethernet AVB Endpoint v5.4 | 2012.1 | 14.1 | AXI4-Lite AXI-Stream |
| 25G IEEE 802.3by Reed-Solomon Forward Error Correction v1.0 | 2016.1 | AXI4-Lite | |
| 50G IEEE 802.3 Reed-Solomon Forward Error Correction v1.0 | 2016.4 | AXI4-Lite | |
| 100G IEEE 802.3bj Reed-Solomon Forward Error Correction v1.0 | 2017.3 | AXI4-Lite | |
| Tri-mode Ethernet Media Access Controller (TEMAC) v9.0 | 2017.3 | 14.4 (v5.5) | AXI4-Lite AXI4-Stream |
| USXGMII Subsystem v1.0 | 2017.3 | AXI4-Lite AXI4-Stream |
|
| Virtex 6 Embedded Tri-mode Ethernet MAC Wrapper v2.3 | 14.1 | AXI4-Lite AXI4-Stream |
|
| Error Correction | |||
| 3GPP Mixed Mode Turbo Decoder v2.0 | 2015.4 | 14.1 (v1.0) | AXI4-Stream |
| Convolutional Encoder v9.0 | 2014.1 | 14.3 (v8.0) | AXI4-Stream |
| Interlaver/De-interleaver v8.0 | 2015.4 | 14.2 (v7.1) | AXI4-Stream |
| Reed Solomon Decoder v9.0 | 2014.1 | 14.1 (v8.0) | AXI4-Stream |
| Reed Solomon Encoder v9.0 | 2014.1 | 14.1 (v8.0) | AXI4-Stream |
| Viterbi Decoder v9.1 | 2015.4 | 14.4 (v8.0) | AXI4-Stream |
| Serial Interface | |||
| Aurora 8B/10B v11.2 | 2017.3 | 14.4 (v8.3) | AXI4-Stream |
| Aurora 64B/66B v11.3 | 2017.3 | 14.4 (v7.2) | AXI4-Stream |
| Wireless | |||
| 3GPP LTE Channel Estimator v2.0 | 2014.4 | 14.3 (v1.1) | AXI4-Stream |
| 3GPP LTE MIMO Decoder v3.0 | 2015.4 | 13.2 (v2.1) | AXI4-Stream |
| 3GPP LTE MIMO Encoder v4.0 | 2014.2 | 14.1 (v3.0) | AXI4-Stream |
| 3GPP Mixed Mode Turbo Decoder v2.0 | 2015.4 | 14.1 (v1.0) | AXI4-Stream |
| 3GPP LTE PUCCH Receiver v2.0 | 2014.1 | 13.4 (v1.0) | AXI4-Stream |
| 3GPP LTE DL Channel Encoder v3.0 | 2017.1 | 14.1 (v2.2) | AXI4-Stream |
| 3GPP LTE UL Channel Decoder v4.0 | 2016.3 | 14.1 (v3.0) | AXI4 AXI4-Stream |
| CPRI v8.8 | 2017.3 | 14.6 (v6.1) | AXI4-Lite |
| Digital Pre-Distortion (DPD) v8.1 | 2017.2 | 14.3 (V5.0) | AXI4 AXI4-Stream AXI4-Lite |
| DUC/DDC Compiler v3.0 | 2015.4 | 14.3 | AXI4-Stream |
| JEDS204 v7.2 | 2017.3 | 14.6 (V3.2) | AXI4-Stream AXI4-Lite |
| JEDS204C v2.0 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| Peak Cancellation Crest Factor Reduction (PC-CFR) v6.1 | 2016.3 | 14.4 (v3.1) | AXI4-Stream AXI4-Lite |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| CIC Compiler v4.0 | 2016.3 | 14.1 (v3.0) | AXI4-Stream |
| CORDIC v6.0 | 2017.3 | 14.1 (v5.0) | AXI4-Stream |
| DDS Compiler v6.0 | 2015.4 | 14.1 (v5.0) | AXI4-Stream |
| Fast Fourier Transform (FFT) v9.0 | 2017.3 | 14.1 (v8.0) | AXI4-Stream |
| FIR Compiler v7.2 | 2015.2 | 14.1 (v6. |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| Core Connect | |||
| AHB Lite to AXI Bridge v3.0 | 2014.1 | EDK 14.3 | AXI4-Lite |
| AXI to PLBV46 Bridge v2.02a | 2012.2 | EDK 14.2 | AXI4 AXI4-Lite |
AXI Quad SPI v3.2 |
2017.1 | 14.4 | AXI4 AXI4-Lite |
| PLBV46 to AXI Bridge v2.01a | 2012.2 | EDK 14.2 (v2.00a) | AXI4 AXI4-Lite |
| Debug and Trace | |||
| ChipScope AXI Monitor v3.05a | EDK 14.2 | AXI4 AXI4-Stream AXI4-Lite |
|
| FPGA Reconfiguration | |||
| AXI Hardware ICAP v3.0 | 2016.3 | EDK 14.2 (v2.03a) | AXI4-Lite |
| Memory Interface | |||
| AXI BRAM Interface Controller v4.0 | 2016.3 | EDK 14.2 | AXI4 AXI4-Lite |
| AXI External Memory Controller v3.0 | 2017.1 | 14.4 (v1.03b) | AXI4 AXI4-Lite |
| AXI Spartan-6 DDRX Memory Controllerv1.05a | 12.4 | AXI4 | |
| AXI Streaming FIFO v4.1 | 2016.1 | 14.4 | AXI4 AXI4-Stream AXI4-Lite |
| AXI System ACE Interface Controllerv1.01a | 13.2 | AXI4-Lite | |
| AXI System Cache v4.0 | 2017.1 | 14.4 | AXI4 AXI4-Lite |
| Peripheral Controller | |||
| AXI External Peripheral Controller v2.0 | 2016.3 | EDK 14.1 (v1.00a) | AXI4-Lite |
| Peripheral Interface | |||
| AXI System Monitor Analog/Digital Converter v2.00a | 13.1 | AXI4-Lite | |
| Peripheral (Networking) | |||
| AXI 1G/2.5G Ethernet Subsystem v7.1 (ISE v3.01a) | 2017.3 | 14.1 | AXI4-Stream AXI4-Lite |
| AXI Ethernet Lite v3.0 (ISE v1.01b) |
2014.3 | EDK 14.1 | AXI4 AXI4-Lite |
| AXI Timer/Counter v2.0 | 2016.3 | 14.3 | AXI4-Lite |
| Peripheral (UART, SPI, IIC, GPIO, Other) | |||
| AXI CAN v1.03a | ISE/EDK 13.2 | AXI4-Lite | |
| AXI General Purpose IO v2.0 (EDK v1.01b) |
2016.3 | EDK 14.1 | AXI4-Lite |
| AXI IIC Bus Interface v2.0 (EDK v1.02a) |
2016.3 | EDK 14.1 | AXI4-Lite |
| AXI Memory Mapped to PCI Express® (PCIe®) Gen2 v2.8 ( ISE v1.06a) |
2017.3 | 14.4 | AXI4 |
| AXI Thin Film Transister (TFT) Controllerv2.0 | 2015.4 | AXI4 AXI4-Lite |
|
| AXI UART 16550 v2.0 (EDK v1.01a) |
2016.3 | EDK 14.2 | AXI4-Lite |
| AXI UART Lite v2.0 (EDK v1.02a) |
2017.1 | EDK 14.2 | AXI4-Lite |
| AXI USB 2.0 Device Controller v4.0 (ISE v3.02a) |
2015.4 | 14.3 | AXI4 |
| AXI Watchdog Timer (WDT) v3.0 (EDK v1.01a) |
2017.3 | EDK 14.2 | AXI4-Lite |
| AXI XADC v2.0 (EDK v1.00a) |
2013.1 | EDK 14.3 | AXI4-Lite |
| Processor Interface | |||
| AXI to APB Bridge v3.0 (EDK v1.01a) |
2015.4 | EDK 14.2 | AXI4-Lite |
| AXI to AXI Connector v1.00a | 12.4 | AXI4 AXI4-Lite |
|
| AXI Interrupt Controller v4.1 (EDK v1.04a) |
2017.3 | EDK 14.6 | AXI4-Lite |
| AXI Lite IPIF v2.0 (EDK v1.01a) |
2016.1 | EDK 14.1 | AXI4-Lite |
| AXI Slave Burst v2.0 (EDK v1.00b) |
2013.1 | EDK 14.2 | AXI4 |
| LogiCORE™ Mailbox v2.1 | 2017.3 | 14.4 | AXI4-Stream AXI4-Lite |
| LogiCORE IP Mutex v2.1 ( ISE v1.00a) |
2015.4 | 14.3 | AXI4-Lite |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| Debug and Verification | |||
| AXI Protocol Checker v1.1 | 2013.4 | AXI4 AXI4-Lite |
|
| AXI4-Stream Protocol Checker v2.0 | 2017.3 | AXI4-Stream | |
| ChipScope™ AXI Monitor v3.05a | 2012.2 | 14.2 | AXI4 AXI4-Stream AXI4-Lite |
| JTAG to AXI Master v1.2 | 2016.3 | AXI4 AXI4-Lite |
|
| Partial Reconfiguration Controller v1.2 | 2017.3 | 14.4 | AXI4-Stream AXI4-Lite |
| IO Interfaces | |||
| Clocking Wizard v5.4 (ISE v4.4) |
2017.3 | 14.4 | AXI4-Lite |
| System Management Wizard v1.3 | 2017.1 | AXI4-Lite | |
| XADC Wizard v3.3 (ISE v2.0) |
2016.3 | 14.2 | AXI4-Stream AXI4-Lite |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| AXI Datamover v5.1 (ISE v4.02a) |
2015.4 | ISE/EDK 14.4 | AXI4 AXI4-Stream |
| AXI Central DMA Controller v4.1 (EDK v3.04a) |
2017.1 | EDK 14.4 | AXI4 AXI4-Lite |
| AXI Chip2Chip v5.0 (ISE/EDK v3.00a) |
2017.3 | ISE/EDK 14.4 | AXI4 AXI4-Lite |
| AXI DMA Controller v7.1 (ISE/EDK v6.03a) |
2017.3 | ISE/EDK 14.4 | AXI4 AXI4-Stream AXI4-Lite |
| AXI Exerciser v4.00a | 2012.4 | EDK 14.4 | AXI4 |
| AXI Interconnect v2.1 (ISE/EDK v1.06a) |
2017.1 | ISE/EDK 14.1 | AXI4 AXI4-Lite |
| AXI Memory Mapped to Stream Mapper v1.1 | 2017.1 | AXI4 AXI4-Stream |
|
| AXI Performance Monitor v5.0 (EDK v3.00a) |
2017.3 | EDK 14.4 | AXI4 AXI4-Stream AXI4-Lite |
| AXI4-Steam Accelerator Adapter v2.1 | 2015.1 | AXI4-Stream AXI4-Lite |
|
| AXI4 Stream Interconnect v1.1 | 2017.3 | AXI4-Stream | |
| AXI4 Stream Infrastructure v2.2 | 2017.1 | AXI-4 Stream AXI4-Lite |
|
| AXI4 Traffic Generator v3.0 (ISE v1.1) |
2017.3 | AXI4 AXI4-Stream AXI4-Lite |
|
| AXI Virtual FIFO Controller v2.0 (ISE v1..1) |
2015.4 | 14.2 | AXI4 AXI4-Stream |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| Complex Multiplier v6.0 (ISE v5.0) |
2014.1 | 14.1 | AXI4-Stream |
| Divider Generator v5.1 | 2016.3 | 14.1 | AXI4-Stream |
| Floating Point Operator v7.1 (ISE v6.1) |
2017.3 | 14.2 | AXI4-Stream |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| Block Memory Generator v8.4 (ISE v8.2) |
2017.3 | 14.3 / 14.4 | AXI4 AXI4-Lite |
| FIFO Generator v13.2 (ISE v9.3) |
2017.3 | 14.3 / 14.4 | AXI4 AXI4-Stream AXI4-Lite |
| Memory Interface Generator (MIG) UltraScale v6.0 7 Series v2.2 |
2014.2 | 14.5 | AXI4 |
| Core | Required Vivado™ Version | Required ISE™ Version | AXI Interface Support |
| AXI Bridge for PCI Express (PCIe) Gen3 Subsystem v3.0 | 2017.3 | AXI4 | |
| AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 | 2017.3 | AXI4 | |
| UltraScale™ FPGAs Gen3 Integrated Block for PCI Express® (PCIe®) v4.4 | 2017.3 | AXI4-Stream | |
| Virtex™ 7 FPGA Gen3 Integrated Block for PCI Express (PCIe) v4.3 (ISE v1.4) |
2017.3 | 14.4 | AXI4-Stream |
| 7 Series Integrated Block for PCI Express (PCIe) Gen2 v3.3 (ISE v1.8) |
2017.3 | 14.4 | AXI4-Stream |
| DisplayPort™ Subsystem v2.1 | 2017.3 | AXI4-Stream AXI4-Lite |
|
| DisplayPort v7.0 (ISE V3.2) |
2017.1 | 14.2 | AXI4-Stream AXI4-Lite |
| DisplayPort with Audio (SPDIF) v2.0 (ISE v1.1) |
2014.1 | 14.2 | AXI4-Stream AXI4-Lite |
| Serial RapidIO IP Core Gen 2 v4.0 (ISE v1.6) |
2017.1 | 14.4 | AXI4-Stream AXI4-Lite |
| Spartan 6 FPGA Integrated Endpoint Block for PCI Express v2.4 | 13.4 | AXI4-Stream AXI4-Lite |
|
| SPDIF Controller v2.0 (ISE v1.2) |
2015.4 | 14.4 | AXI4-Stream AXI4-Lite |
| Virtex 6 Integrated Block for PCI Express v2.5 | 14.1 | AXI4-Stream |